Variability-aware architectures based on hardware redundancy for nanoscale reliable computation

During the last decades, human beings have experienced a significant enhancement in the quality of life thanks in large part to the fast evolution of Integrated Circuits (IC). This unprecedented technological race, along with its significant economic impact, has been grounded on the production of complex processing systems from highly reliable compounding devices. However, the fundamental assumption of nearly ideal devices, which has been true within the past CMOS technology generations, today seems to be coming to an end. In fact, as MOSFET technology scales into nanoscale regime it approaches to fundamental physical limits and starts experiencing higher levels of variability, performance degradation, and higher rates of manufacturing defects. On the other hand, ICs with increasing number of transistors require a decrease in the failure rate per device in order to maintain the overall chip reliability. As a result, it is becoming increasingly important today the development of circuit architectures capable of providing reliable computation while tolerating high levels of variability and defect rates. The main objective of this thesis is to analyze and propose new fault-tolerant architectures based on redundancy for future technologies. Our research is founded on the principles of redundancy established by von Neumann in the 1950s and extends them to three new dimensions: 1. Heterogeneity: Most of the works on fault-tolerant architectures based on redundancy assume homogeneous variability in the replicas like von Neumann's original work. Instead, we explore the possibilities of redundancy when heterogeneity between replicas is taken into account. In this sense, we propose compensating mechanisms that select the weighting of the redundant information to maximize the overall reliability. 2. Asynchrony: Each of the replicas of a redundant system may have associated different processing delays due to variability and degradation; especially in future nanotechnologies. If we design our system to work locally in asynchronous mode then we may consider different voting policies to deal with the redundant information. Depending on how many replicas we collect before taking a decision we can obtain different trade-off between processing delay and reliability. We propose a mechanism for providing these facilities and analyze and simulate its operation. 3. Hierarchy: Finally, we explore the possibilities of redundancy applied at different hierarchy layers of complex processing systems. We propose to distribute redundancy across the various hierarchy layers and analyze the benefits that can be obtained. Drawing on the scenario of future ICs technologies, we push the concept of redundancy to its fullest expression through the study of realistic nano-device architectures. Most of the redundant architectures considered so far do not face properly the era of Terascale Computing and the nanotechnology trends. Since von Neumann applied for the first time redundancy at electronic circuits, never until now effects as common in nanoelectronics as degradation and interconnection failures have been treated directly from the standpoint of redundancy. In this thesis we address in a comprehensive manner the reliability of digital processing systems in the upcoming technology generations

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a Fault-Tolerant Nanoscale architecture based on the implementation of logic systems with averaging cells linear threshold gates (AC-LTG). The sensitivity of the gates in relation with manufacturing and environment deviation is investigated and compared with the well known NAND multiplexing concept, showing that the AC-LTG is a valuable alternative in specific nanoscale conditions.Peer ReviewedPostprint (published version

Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm

Best DCIS Paper Award 20123T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.Peer ReviewedAward-winningPreprin

Extending the fundamental error bounds for asymmetric error reliable computation

Future computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging problems of this research area consists in finding the fundamental error bounds beyond which reliable computation is not possible. In the literature we can find the exact error threshold for circuits built out of noisy NAND gates under the von Neumann's probabilistic computing framework. In this paper we extend this result for asymmetric error designs and demonstrate that it is possible to compute reliably with 2-input noisy NAND gates beyond the well known error bound: ∈* = (3 - √7)/4.Peer ReviewedPostprint (published version

Reliability and performance tunable architecture: the partially asynchronous R-Fold modular redundancy (pA-RMR)

The R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results with a majority criterion. In this analytic study, we extend this conventional approach by introducing the time dimension in the RMR design. Indeed, the asynchronous nature of future nanoelectronic computing systems is taken into account by introducing the partially asynchronous RMR (pA-RMR) structure whose main feature is to detect the arrival of each input signal from the replicas based on the use of tokens. The voter behavior is modified in such a way that it sets the output result after a determined number of token arrivals. By doing this, we are adding a second degree of freedom to the RMR structure, which not only has a configurable size (R replicas), but also allows modifying the number of tokens it waits before giving an output. As a consequence of this seemingly simple change, we are able to exploit new possibilities of this redundant structure. This second degree of freedom allows choosing between system reliability and performance during operation. The number of available replicas in the pA-RMR architecture determines the maximum reliability achievable, while the voting policy allows us to adapt the structure to different design requirements and achieve the desired balance between reliability and performance.Peer ReviewedPostprint (published version

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs). We compare the tolerance to manufacturing and environment deviation of our approach and the well known NAND multiplexing technique. We show that the AC-LTG is a valuable alternative in specific nanoscale conditions.Peer ReviewedPostprint (published version

Flips in low codimension Classification and quantitative theory

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN005370 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a Fault-Tolerant Nanoscale architecture based on the implementation of logic systems with averaging cells linear threshold gates (AC-LTG). The sensitivity of the gates in relation with manufacturing and environment deviation is investigated and compared with the well known NAND multiplexing concept, showing that the AC-LTG is a valuable alternative in specific nanoscale conditions.Peer Reviewe

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs). We compare the tolerance to manufacturing and environment deviation of our approach and the well known NAND multiplexing technique. We show that the AC-LTG is a valuable alternative in specific nanoscale conditions.Peer Reviewe

Extending the fundamental error bounds for asymmetric error reliable computation

Future computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging problems of this research area consists in finding the fundamental error bounds beyond which reliable computation is not possible. In the literature we can find the exact error threshold for circuits built out of noisy NAND gates under the von Neumann's probabilistic computing framework. In this paper we extend this result for asymmetric error designs and demonstrate that it is possible to compute reliably with 2-input noisy NAND gates beyond the well known error bound: ∈* = (3 - √7)/4.Peer Reviewe